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data sheet august 1999 lg1600fxh clock and data regenerator figure 1. lg1600fxh open view features n integrated clock recovery and data retiming n surface-mount package n single ecl supply n robust fpll design n operation up to ber = 1e C3 n sonet/sdh compatible loss of signal alarm n high effective q allows long run lengths n jitter tolerance exceeding itu-t/bellcore n low clock jitter generation: typical <0.005 ui n standard and custom data rates 0.50 gbits/s5.5 gbits/s n complementary 50 w i/os applications n sonet/sdh receiver terminals and regenerators oc-12 through oc-96/stm-4 through stm-32 n sonet/sdh test equipment n proprietary bit rate systems n digital video transmission n clock doublers and quadruplers
data sheet lg1600fxh clock and data regenerator august 1999 2 lucent technologies inc. functional description the lg1600fxh clock and data regenerator (cdr) is a compact, single device solution to clock recovery and data retiming in high-speed communication sys- tems such as fiber-optic data links and long-span fiber- optic regenerators and terminals. using frequency and phase-lock loop (fpll) techniques, the device regen- erates clean clock and error-free data signals from a nonreturn-to-zero (nrz) data input, corrupted by jitter and intersymbol interference. the lg1600fxh exceeds itu-t/bellcore jitter tolerance requirements for sonet/sdh systems. the device houses two integrated circuits on an alu- mina substrate inside a hermetically sealed 3 cm 3cm (1.2in. 1.2 in.) surface-mount package: a gaas ic that contains the high-speed part of an fpll as well as a highly sensitive decision circuit; and a silicon bipo- lar ic that contains a loop filter, acquisition, and signal detect circuitry. the two ac-coupled complementary data inputs can be driven differentially as well as single ended. a dc feed- back voltage v Cfb maintains a data input threshold v Cth (decision level) that is optimum for a wide range of 50% duty cycle input levels (connect to v Cth ). if needed, the user can supply an external threshold to compensate for different mark densities or distorted input signals (see figure 10). regenerated clock and data are available from comple- mentary outputs that can either be ac coupled, to pro- vide 50 w output match, or dc coupled with 50 w to ground at the receiving end. the second-order pll filter bandwidth is set by the user with an external resistor between pin 11 and ground (required). an internal capacitor provides suffi- cient pll damping for most applications. in critical applications, pll damping can be increased using an external capacitor between pins 9 and 11. the device is powered by a single C5.2 v ecl compat- ible supply and typically consumes 1.5 w. the lg1600fxh comes in standard bit rates, but can be factory tuned for any rate between 500 mbits/s and 5500 mbits/s. a test fixture (TF1004A) with sma connectors is avail- able to allow quick evaluation of the lg1600fxh. theory of operation a digital regenerator has the task of retransmitting a bit stream that is received from a remote source with the same fidelity at which it was originally transmitted. two basic properties of the digital signal need to be restored: the timing of the transitions between the bits and the value of each bit. 12-3225(f)r.6 figure 2. lg1600fxh block diagram vco q d v + clko v C clko 31 26 d freq. & 90 loop control & 11 9 7 v ref c ext r ext los v Cth 51 v Cfb 48 55 60 65 v Cin v +in v +fb 0.047 m f 0.047 m f 0.047 m f 0.047 m f 1 k w 50 w 25 k w 50 w 25 k w 1 k w 43 38 v + out v C out v ss 35 0.047 m f 0.047 m f signal detect phase detect. 0
data sheet august 1999 lg1600fxh clock and data regenerator 3 lucent technologies inc. theory of operation (continued) consequently, the timing information that is present in the data needs to be extracted and a decision as to the value of each bit must be made. both timing instant and decision levels are critical, since the economics of data transmission dictate the largest distance possible between transmitter and receiver. a practically closed data eye can therefore be expected at the output of the receiver, allowing only a small decision window. an added complication in nonreturn-to-zero (nrz) sys- tems is the absence of clock component in the data signal itself. practical clock recovery circuits have used a combination of nonlinear processing to extract a spectral component at the clock frequency and narrow- band filtering using a saw filter or dielectric resonator. the relative bandwidth of such a filter must be on the order of a few tenths of a percent to minimize the data pattern dependence of the resulting clock. temperature behavior of the passband characteristics, such as group delay, must be tightly matched to that of the data path. these extreme requirements make such a dis- crete design very difficult to manufacture at gbits/s data rates. the lg1600fxh clock and data regenerator relies on phase-lock loop techniques, rather than passive filter- ing. the filter properties of a pll are determined at low frequencies where parasitic elements play only a minor roll and stability is easily maintained. furthermore, the reference frequency is determined by the data rate itself, rather than by the physical properties of a band- pass filter. although plls can eliminate some of the shortcomings of passive bandpass filters used in clock recovery cir- cuits, care was taken in the design of the lg1600fxh to preserve desired properties such as linearity of the jitter characteristics. a linear jitter transfer makes it a lot easier for the system designer to predict the overall performance of a link. as a result, the architecture chosen for the device is not basically different from the conventional clock recovery circuit. a transition detector extracts a pulse train from the incoming data signal which is used as a reference signal for a pll. the transition pulse train can be seen as a clock signal that is modulated with the instanta- neous transition density of the data signal. the pll locks onto the frequency and phase of this pulse train and freewheels during times when transitions are absent. the lg1600fxh features dual phase detec- tors; one driven by an in-phase clock which is also driv- ing the decision circuit flip-flop, the other is driven by a quadrature clock. the phase detectors produce a zero output when their respective clocks are centered with respect to the transition pulses. 12-3226(f)r.3 figure 3. frequency and phase detector for a transition pulse of half the width of the bit period, the timing diagram of figure 4 shows how the in-phase clock ends up in the center of the data eye when the quadrature-phase detector output is forced to zero by the loop. the (patented) transition detector is com- prised of an (active) circulator, a shorted stub, and an exclusive-or gate. the circulator/stub combination produces a delayed version of the data. a transition at the input of the circuit results in an output pulse from the exclusive-or gate whose width equals the return delay of the stub. the stub is tuned for a given bit rate and can be adjusted so that the in-phase clock is exactly centered in the error-free phase range of the retiming flip-flop. 12-3227(f)r.2 figure 4. timing diagram pdq pdi logic to flip-flop from vco 90 0 transition pulse data circulator delayed data stub fpd out 90 0 transition delayed data 1/2 t 1/4 t data pulse clock clock t
data sheet lg1600fxh clock and data regenerator august 1999 4 lucent technologies inc. theory of operation (continued) 12-3228(f)r.4 figure 5. frequency and phase detector characteristics the frequency detector is not a separate function but an integral part of the phase-lock loop. any transition between frequency and phase acquisition is completely avoided. figure 5 shows the output characteristics of the fpd, which is essentially an extended range phase detector. the two quadrature clock phases are used to produce hysteresis, which extends the phase detector range to 270. the extended range gives the phase detector a static frequency sensitivity as demonstrated in figure 6. for clock frequencies lower than the bit rate (the phase is increasing), the top trajectory of the dia- gram in figure 6 is followed. when the vco frequency exceeds the bit rate, the lower trajectory applies. since the linear part of the phase detector produces a net- zero output, in the first instance, positive pulses are fed into the loop filter increasing the vco frequency, while in the latter case, the fpd produces negative pulses. the wide, 540 range of the phase detector is also responsible for the high jitter tolerance of the lg1600fxh and an associated immunity to cycle slip under high jitter conditions. the clock can be momen- tarily misaligned as much as 270 but still return to its original position. this property is extremely important in synchronous systems, since a cycle slip would cause misalignment of the demultiplexer following the circuit resulting in a loss of frame condition. the lg1600fxh can handle bit error rates up to 1e C3 as a result of low- frequency jitter. 12-3229(f)r.4 figure 6. frequency detector operation pll dimensioning the lg1600fxh cdr employs a heavily damped second order phase-lock loop. a linear model of this pll is depicted in figure 7. the conventional second- order equation describing the jitter transfer of the pll is shown below: where j i and j o denote the input and output phase, respectively, v is the pll damping ratio and w n is the natural frequency. for most clock recovery applications a very high damping is required, that renders the pll essentially as a first-order system with a slight peaking that is generally undesirable. the second-order equa- tion above does not provide much insight into the peak- ing and bandwidth parameters. 12-3230(f)r.5 figure 7. phase-lock loop linear model C360 C180 0 180 360 fpd out phase fpd out fpd out time time a. fck < f b b. fck > f b hs () j o j i ----- - s () 2 vw n s w n 2 + s 2 2 vw n s w n 2 ++ ------------------------------------------ == j i j o ko vco kd phase detector sum of internal and external loop filter capacitance c rx
data sheet august 1999 lg1600fxh clock and data regenerator 5 lucent technologies inc. theory of operation (continued) a more useful expression of the pll characteristics is the following * : the jitter transfer is now directly expressed in the phys- ical loop gain pole product, w b , and the loop filter time constant, t . damping ratio, v, and natural frequency, w n , simply relate to these two parameters as follows: and * wolaver, d.h., phase-locked loop circuit design , prentice hall, 1991. hs () w b 1 1 s t ----- + ? ?? s w b 1 1 s t ----- + ? ?? + ------------------------------------- - = vw b t 0.5 = w n w n t = for moderate damping v > 2.5 (w b t < 0.1), the C3 db bandwidth of the pll can be approximated by the loop gain pole product: j bw ? w b = k d r x k o while the jitter peaking can be expressed in terms of the product of pll bandwidth and loop filter time con- stant: as the last two expressions make clear, the pll band- width is controlled by the value of the external resistor (see figure 8), while the peaking depends both on the resistor value (quadratically) and total loop filter capac- itance. hs () max 1 1 w b t --------- + ? 1 1 r x 2 ck d k o ------------------------- - + = 12-3231(f)r.412-3232(f)r.4 figure 8. jitter bandwidth vs. external resistor value 0 50 100 200 250 0.0 0.2 0.6 0.8 1.0 1.2 rx ( w ) 0.4 150 a. lg1600fxh0622 (cx = 0.15 m f) 10 c 70 c 25 c j bw (mhz) 0 50 100 200 250 0.0 0.6 1.8 2.4 3.0 3.6 rx ( w ) 1.2 150 b. lg1600fxh2488 (cx = 0) 10 c j bw (mhz) 25 c 70 c
data sheet lg1600fxh clock and data regenerator august 1999 6 lucent technologies inc. pin information the pinout for the lg1600fxh is shown in figure 9. 12-3233(f)r.1 figure 9. pin diagram dnc dnc v ref c ext r ext los dnc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 1 4 7 9 11 14 17 18 26 31 34 v Cclko v +clko nic gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v Cth v Cfb v +out v Cout v ss gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 51 48 43 38 35 68 65 nic v +fb v +in v Cin gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 60 55 52 2 3 5 6 8 10 12 13 15 16 19 20 21 22 23 24 25 27 28 29 30 32 33 36 37 39 40 41 42 44 45 46 47 49 50 53 54 56 57 58 59 67 66 64 63 62 61
data sheet august 1999 lg1600fxh clock and data regenerator 7 lucent technologies inc. pin information (continued) the pin descriptions for the lg1600fxh are given in table 1. table 1. pin descriptions pin symbol name/description 1, 4, 17 dnc do not connect. internal test point or reserved for future use. 7v ref reference voltage. nominally C3.2 v. can be used to bias lg1605dxb (see data sheet). load 3 10 k w . 9c ext terminal for optional external capacitor to increase pll damping (normally not connected). 11 r ext terminal for external resistor to set pll bandwidth (required). 14 los loss of signal indicator. provides approximately 1 ma sink current with data signal present, can interface to cmos, ttl when connected to logic v dd through a 10 k w resistor. normally grounded when not used. 26 v Cclko recovered clock out. ac couple or terminate into 50 w to gnd. 31 v +clko recovered clock out. ac couple or terminate into 50 w to gnd. 35 v ss supply voltage. C5.2 vdc nominal. warning: connecting a positive voltage to this pin will permanently damage the device. 38 v Cout regenerated data out. ac couple or terminate into 50 w to gnd. 43 v +out regenerated data out. ac couple or terminate into 50 w to gnd. 48 v Cfb dc feedback voltage. connect to v Cth . 51 v Cth input threshold voltage. connect to v Cfb . 55 v Cin negative data input. internally ac coupled. 60 v +in positive data input. internally ac coupled. 65 v +fb dc feedback voltage. internally connected; not normally used. 18, 68 nic no internal connection. may be grounded. 2, 3, 5, 6, 8, 10, 12, 13, 15, 16, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 32, 33, 34, 36, 37, 39, 40, 41, 42, 44, 45, 46, 47, 49, 50, 52, 53, 54, 56, 57, 58, 59, 61, 62, 63, 64, 66, 67 gnd ground. connect to top ground plane of coplanar/microstrip circuit board. body gnd ground. does not need to be connected. gnd pins provide all necessary ground connections.
data sheet lg1600fxh clock and data regenerator august 1999 8 lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 2. absolute maximum ratings recommended operating conditions table 3. recommended operating conditions handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent technologies microelectronics group employs a human-body model (hbm) for esd-susceptibility testing and protection design evaluation. the hbm (resistance = 1500 w , capacitance = 100 pf) is used. the hbm esd threshold presented in table 4 was obtained by using these circuit parameters. table 4. esd threshold mounting and connections certain precautions must be taken when using solder. for installation using a constant temperature solder, temper- atures of under 300 c may be employed for periods of time up to 5 seconds, maximum. for installation with a sol- dering iron (battery operated or nonswitching only), the soldering tip temperature should not be greater than 300 c and the soldering time for each lead must not exceed 5 seconds. parameter min max unit supply voltage range (v ss )C70.5v loss of signal bias voltage (v dd )7v power dissipation 2 w voltage (all pins) v ss 0.5 v transient voltage to ac couple pins (v in , r ext )3v storage temperature range C40 125 c operating temperature range C40 100 c parameter symbol min max unit case temperature t case 070c power supply v ss C4.7 C5.7 v hbm esd threshold device voltage lg1600fxh 3 200 v
data sheet august 1999 lg1600fxh clock and data regenerator 9 lucent technologies inc. electrical characteristics t case = 0 c to 70 c, v ss = C4.7 v to C5.7 v, v dd = 5 v, bit rate = f b gbits/s 0.05% nrz and data pattern = 2 23 C 1 prbs, 200 mv v in 800 mv, ber < 1e C9 , unless otherwise indicated. note: minimum and maximum values are testing requirements. typical values are characteristics of the device and are the result of engineering evaluations. typical values are for information purposes only and are not part of the testing requirements. parameter symbol conditions min typ max unit data input voltage v Cin single ended on either input 200 800 mvp-p data input voltage v +in C v Cin differential 200 1600 mvp-p data output voltage v out ac coupled 625 750 900 mvp-p data output voltage v out dc coupled 650 800 900 mvp-p clock output voltage v clko dc coupled 650 750 900 mvp-p clock output voltage v clko ac coupled; f b 3 gbits/s 625 750 900 mvp-p clock output voltage v clko ac coupled; f b > 3 gbits/s 500 600 900 mvp-p output pulse width rela- tive to bit period t = 1/f b pw% t case = 40 c 90 100 110 % clock output duty cycle dc clko t case = 40 c 40 60 % clock/data output transi- tion time t r , t f 20% to 80% 80 100 ps maximum bit error rate ber max jitter modulation @ f b 40 khz, t case = 40 c 1e C3 los output voltage, low v losl r l = 10 k w C1 C0.8 0.5 v los output voltage, high v losh r l = 10 k w , v Cin = 0 v v dd C 0.5 v dd v dd v loss of signal delay t los measured from last data transi- tion, t case = 40 c 10 30 100 s jitter generation j gen 0.0050.01ui jitter transfer bandwidth j bw user adjustable with r x as sug- gested by figure 8, t case = 25 c f b mhz output reference voltage v ref load to ground 3 20 k w C3.4 C3.15 C2.9 v jitter tolerance j tol f mod f b x 40 khz, t case = 40 c f b x 40 khz f mod f b 400 khz, t case = 40 c f mod 3 f b 400 khz, t case = 40 c 1.5 0.6 f b / f mod 0.15 5 2 f b /f mod 0.5 ui ui ui acquisition/recovery time t acq measured from first data transition * , t case = 40 c * parameter guaranteed by design or characterization and not production tested. 600 800 s supply current i ss C5.7 v v ss C4.7 v 290 320 ma
data sheet lg1600fxh clock and data regenerator august 1999 10 lucent technologies inc. test circuit 12-3234(f)r.6 notes: resistor r x determines the pll bandwidth and is required for normal operation. the lg1600fxh differs in this respect from the lg1600axd cdr, which has an internal resistor that sets a minimum bandwidth. the recommended value is 140 w for optimal jitter transfer performance. capacitor c x is optional and can be used to increase the damping of the pll in critical applications. the outputs may be either ac coupled, as indicated, or dc terminated into 50 w . in the first case, good output return loss can be obtained. the latter configuration provides a 0 mv to C800 mv output swing for easy interface to dc-coupled circuits. figure 10. lg1600fxh typical test circuit 500 k w + vco q d v + clko v C clko 31 26 d freq. & phase detect. 0 90 loop control & signal detect 11 14 9 7 v ref c ext r ext los v Cth 51 v Cfb 48 55 60 65 v Cin v +in v +fb 0.047 m f 0.047 m f 0.047 m f 0.047 m f 1 k w 50 w 25 k w 50 w 25 k w 1 k w 43 38 v +out v Cout 35 0.047 m f 50 w 50 w data generator optional threshold control alternative 50 w 50 w optional c a > 0.1 m f/f b v ss 5.2 v + optional c b > 100 pf/f b 50 w 50 w c x optional (see text) r x = 140 w required 0.047 m f 10 k w v dd 5 v + v los v ss
data sheet august 1999 lg1600fxh clock and data regenerator 11 lucent technologies inc. typical performance characteristics figure 11. lg1600fxh typical eye patterns lg1600fxh0553 lg1600fxh2488 lg1600fxh4977
data sheet lg1600fxh clock and data regenerator august 1999 12 lucent technologies inc. typical performance characteristics (continued) 12-3235(f)r.2 figure 12. data clock output timing diagram 0 500 1500 2000 C100 100 200 300 500 bit period (ps) 0 1000 400 output timing (ps) output timing y = 1/4x C 65 v out v+ clko
data sheet august 1999 lg1600fxh clock and data regenerator 13 lucent technologies inc. typical performance characteristics (continued) 12-3236(f)r.3 figure 13. error recovery timing diagram 0 200 400 800 0 100 300 400 500 700 input blanking ( m s) 200 600 600 recovery time ( m s) blanking input output error error recovery 1000 pulse data data signal time
data sheet lg1600fxh clock and data regenerator august 1999 14 lucent technologies inc. typical performance characteristics (continued) 12-3237(f)r.4 figure 14. error recovery test circuit error detector trig out pulse generator ch3 ch2 ch1 lf oscilloscope clk data data clk blnk pattern generator data in data out clk out ch1 ch2 ch3 digitizing oscilloscope mixer
data sheet august 1999 lg1600fxh clock and data regenerator 15 lucent technologies inc. outline diagram 68-pin surface-mount package dimensions are in inches. 12-3350(f).ar.1 0.015 typ 0.050 typ 1.370 0.10 0.010 detail a 0.158 0.010 C0.002 0.030 05 r0.020 detail a +0.005 1 17 18 34 35 51 52 68 1.180 0.590
data sheet lg1600fxh clock and data regenerator august 1999 16 lucent technologies inc. ordering information device code package temperature comcode lg1600fxhxxxx surface-mount package 0 c to 70 c 107236143 lg1600fxh0500 surface-mount package 0 c to 70 c 107914038 lg1600fxh0553 surface-mount package 0 c to 70 c 107236101 lg1600fxh0622 surface-mount package 0 c to 70 c 107339244 lg1600fxh1200 surface-mount package 0 c to 70 c 107841447 lg1600fxh1244 surface-mount package 0 c to 70 c 107386179 lg1600fxh1298 surface-mount package 0 c to 70 c 107236127 lg1600fxh1555 surface-mount package 0 c to 70 c 107914046 lg1600fxh2380 surface-mount package 0 c to 70 c 107236135 lg1600fxh2433 surface-mount package 0 c to 70 c 107645939 lg1600fxh2488 surface-mount package 0 c to 70 c 107081879 lg1600fxh2666 surface-mount package 0 c to 70 c 107386187 lg1600fxh2949 surface-mount package 0 c to 70 c 107385650 lg1600fxh3111 surface-mount package 0 c to 70 c 107394132 lg1600fxh3840 surface-mount package 0 c to 70 c 107840423 lg1600fxh4977 surface-mount package 0 c to 70 c 107081887 lg1600fxh5332 surface-mount package 0 c to 70 c 107081895 TF1004A test fixture 106497621
data sheet august 1999 lg1600fxh clock and data regenerator 17 lucent technologies inc. appendix the test fixture mentioned in the data sheet is sold separately and is described in detail below. 5-7831(f) figure 15. TF1004A test fixture TF1004A test fixture features n sma connectors n easy package placement n good rf performance test fixture functional description the TF1004A test fixture is used to characterize 68-pin surface-mount packages for high-speed fiber-optic commu- nications. the fixture consists of a metallized substrate (ptfe filled material) fastened to a brass base with rf connectors and mounting hardware for the package. the package leads make contact to the circuit traces on the fixture through use of a pressure ring and four finger nuts. the TF1004A is preassembled and fully tested prior to shipment. before use of test fixture n due to possible stress during shipment, sma connectors may be misaligned. n check each sma for continuity. n if necessary, realign and retighten with a 5/64 in. hex key wrench.
data sheet lg1600fxh clock and data regenerator august 1999 18 lucent technologies inc. appendix (continued) instructions for use of test fixture a pair of flat-tip tweezers can be used to insert or remove a package from the test fixture. always wear a grounding strap to prevent esd. 1. to insert a package, remove the four finger nuts and gently lift the pressure ring off of the test fixture. 2. place the pressure ring, cavity side up, on a flat esd safe surface. 3. connect the metal tube to any general-purpose vacuum source with flexible tubing. the vacuum source should be off. 4. place the package, lid down, on a flat esd safe surface. locate pin 1 on the package. 5. insert the package into the pressure ring (lid down) with pin 1 located next to the orientation mark and turn on the vacuum. the vacuum will retain the package in the pressure ring during the following steps. 6. align the vertically conductive material on the circuit board. 7. place the pressure ring down over the alignment pins and gently tighten the finger nuts. 8. remove vacuum, if desired. the vacuum source tubing can be removed for convenience. 5-7832(f)r.1 figure 16. TF1004A connector assignment v +clk v Cclk nic dnc los v Cfb v +out v Cout v ss v Cth dnc dnc v Cin v +in v +fb (48) (43) (38) (35) (51) (55) (60) (1) (4) (7) (11) (9) (14) (17) (18) (26) (31) v ref c ext r ext (65) pin #1 nic = no internal connection dnc = do not connect (##) = package pin number
data sheet august 1999 lg1600fxh clock and data regenerator 19 lucent technologies inc. notes
lg1600fxh clock and data regenerator preliminary data sheet interactive terminal transmission convergence august 1999 for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved printed in u.s.a. august 1999 ds99-186hspl (replaces ds96-237fce)

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